Chip-to-chip communication is commonly implemented with high-speed, point-to-point links such as with differential point-to-point links transmitting differential data signals. Achievable data rates can be affected by voltage and timing margins of the transmitted signals. For example, deviations from specified transmitted voltage swings during operation can result in decreased margins and therefore a decreased data-rate. Unfortunately, it is difficult to control voltage swing levels because they vary with operating environment changes such as with changes in PVT (process, voltage, and temperature) and physical structure such as trace lengths, and the like. Because changes generally affect the various transmitter circuits within a chip the same, chips typically incorporate one or more distributed general (or global) compensation circuits to control multiple transmitter circuits reasonably proximal to the compensation circuit to compensate for such variations.
FIG. 1 shows a conventional multi-bit point-to-point link with global current compensation (I-Comp) and termination resistance compensation (R-Comp) to control (e.g., keep reasonably sufficient) output voltage swing magnitudes in accordance with design specifications. It comprises N transmitter drivers 101 to be coupled to N corresponding receivers (e.g., on a different chip, not shown). Each driver has an associated pair of variable termination resistors to convey differential data signals (Dini, Dini#). Also included is a global current compensation (I-Comp) circuit 103, which uses a reference current (I-Ref) to generate and distribute multiple copies of current, I1 through IN, to each individual TX driver (Tx1 to TxN). The current is used to generate a desired output swing that is also affected by the values of the termination resistors. A global resistance compensation (R-Comp) circuit 105 is also included to generate resistance compensation signals from an R-Ref control resistor.
Transmitter swing specifications are typically determined through system simulations and are set high enough to meet target frequency and bit error rate (BER) objectives under worst case platform and system parameters due to operational, environmental, and/or implementation deviations. The global reference current value is then typically programmed (e.g., via fuses or the like) into the reference circuit 103 to generate a sufficient swing magnitude under these worst case conditions.
Unfortunately, this can be inefficient since in many cases, higher swing levels (and thus higher currents) than are needed are generated. For example, with some platforms, mother board trace impedances (per unit length) can vary +/−12%. The lengths of traces can also vary up to 10%. This can be fairly costly. With some platforms, for example, for every two inches of trace length increase, a Tx swing increase of 100 mV may be required. Accordingly, improved approaches may be desired.